1. Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method thereof which are, in particular, preferably applied to a non-volatile memory having a floating gate.
2. Description of the Related Art
Memory ICs having a function of storing information thereon include non-volatile memories as memory ICs that keep storing the information even when their power sources are cut off. Further, there are, as rewritable non-volatile memories, EPROMs which electrically write information and erase it by ultraviolet irradiation, EEPROMs which both write and erase electrically, and further flash memories which combine those advantages and so on, which are used in various applications.
Each of these rewritable non-volatile memories is provided with a floating gate to be able to perform write and erase by injecting and drawing carriers to and from the floating gate.
An example of a conventional non-volatile memory is explained here.
FIG. 28 to FIG. 30 show an example of a conventional NOR-type non-volatile memory. FIG. 28 shows its plan view, FIG. 29 shows an equivalent circuit diagram thereof, and FIG. 30 shows a schematic cross-sectional view of a memory cell between III and III shown in FIG. 28.
As shown in FIG. 28 and FIG. 29, in the conventional NOR-type non-volatile memory, memory cells 100 are formed at cross portions where word lines (WL1 to WL4) and bit lines (BL1 to BL4) cross each other at right angles, in which one floating gate 101 is disposed at each of the memory cells.
The word lines (WL1 to WL4) serve as control gates, the bit lines (BL1 to BL4) serve as drains, common source regions are provided between the word lines (WL1 to WL4), and one drain contact is provided for every two memory cells.
As shown in the schematic cross-sectional view in FIG. 30, in the conventional non-volatile memory, the floating gate 101 is formed above a Si substrate 102 through a silicon oxide film (SiO2) 105. This floating gate 101 is disposed above a source 103 and a drain 104 to inject and draw carriers to and from the source 103 and the drain 104.
On the floating gate 101, an ONO film 106 and a control gate 107 are formed, thereby constituting a memory cell. The memory cell having the source 103 formed of an n-type diffusion layer with an LDD structure and the drain formed of an n-type diffusion layer with a single drain structure, is shown in this example.
In recent years, in order to increase the integration of the above-described non-volatile memory, improvements have been made in a direction of microfabrication in which the floating gate is formed in a complex three-dimensional structure or the like to increase the effective area of the floating gate, but such improvements actually have a limitation because of a limit on manufacturing such as a limit on light exposure or the like.
In addition, in the conventional NOR-type nonvolatile memory, since one drain contact is required for every two memory cells, a unit memory cell increases in area, giving rise to a problem that the memory cannot be increased in integration.